Memory devices such as a DRAM are operated with a power supply voltage supplied from a power management IC. The power management IC minimizes power consumption by changing the supply capability of the power supply voltage according to the current operation status of a DRAM. For example, during a period where a DRAM is performing a read operation or a write operation, the supply capability of the power supply voltage of the power management IC is set to be relatively large, and when the DRAM is in a standby mode, the supply capability of the power supply voltage of the power management IC is set to be relatively small.
However, because memory cells of a DRAM are volatile, even when the DRAM is in a standby mode, it is necessary to restore information held in the memory cells by periodically performing a refresh operation. Therefore, when the DRAM is in a standby mode, the power supply capability of the power management IC is set as the power supply capability required for the refresh operation.